Yes Dieter,

but the main problem is the WR# Signal. The design has to take care of it and during power down modes, it has to keep WR# high, regardless what ever happens on the WR# from the CPU. Otherwise you cannot be shure that the data will be safe.
The second problem is the current that goes from the ram-pins to the CPU via adressbus and/or databus. some CPUs have diodes on these pins to protect them against over voltage. now imagine the cpu has no voltage and the ram has. In this case the voltage of the ram is higher than the voltage of the cpu and the value is higher than Vf of these diodes. So the cpu can get current through these diodes to its vcc pins. well the current is not high enough for the cpu but it is a current that comes out of the battery.
What i want to say is that it is not easy to implement a power fail safe NVRAM. And that is the reason why we use NVRAM from Dallas or others, because they have these proctions build in. Count the cost for SRAM Battery and ciruit together and compare it with the price for a NVRAM inclunding all.

Michael