Hi Kamall,

The main problem on this is, how can I protect data during
power down,
power up,
power low,
power high,
short power breaks,
power with ESD pulses,
...
Also how can I protect data against altering during all
possible power conditions.

Its real a big problem and I know no good solution.

The not cheap Dallas NVRAM can work in most of this cases.
But on all SRAM a write cycle is very short and to easy to
initiate.

My suggestion to store data during power off:

The best results I get on using Flash (e.g. AT29C512)
or serial EEPROM (e.g. 24C64).
They need a 3 byte write enable sequence or
a long serial data stream to initiate write cycles.
This give the highest protection against crazy CPU
during several power conditions.
They also internal protected during power up or low power.


Regards,
Peter