The guys at SiLabs took a look at the table on page 247 of the abovementioned HCS08 manual, and then implemented it literally in VHDL/Verilog. As we already know from Russ's first steps, Verilog does not quite like "... and you can assume no care for the unspecified inputs so that the result will be optimal..." so maybe their tool simply assumed "...and do nothing for the rest".

On the other hand, in the biblical times of hand optimised vanilla 8051, I assume, they did exactly what they described - compared, generated constants, and run the adder conditionally twice - once for each nibble which had to be adjusted.

JW