| ??? 10/02/07 23:18 Read: times |
#145273 - Yes, that's fine ... well, maybe ... Responding to: ???'s previous message |
Jan Waclawek said:
Richard Erlacher said:
If you have no guidance from the manufacturer, and no statistical evidence, how can you presume to predict what a component will do as its supply voltage falls out of specified limits? What are the underlying assumptions, and what is their source? Well, the assumption is that CMOS circuits consists of PMOS and NMOS (both of enhancement type); and the source is ... ehm... well somewhere in the misty past, the basic (you would perhaps say 101) electronic devices lectures I attended... :-) I may have attended some of those lectures too, though in seminars, and not as a student. The first thing I learned, though, was that different regions of a die may be at considerably different voltages, (~+/- 0.3 volts) and that if you want to model them in operation, you have to "monte-carlo" the Vdd and Vss. IC makers take great pains to minimize this problem, but ... Look, this is all easy and simple, if you want, throw in a CMOS inverter into SPICE and try to wiggle VCC... I think even slightly more complicated structures such as a flipflop can be modelled relatively easily.
Richard Erlacher said:
The trip voltage for the nWE lockout of the BBRAMs I used is considerably higher than 2V. Nevertheless, I observed MCU activity during RESET asserted by a MAX1232 during a very long (not measured) decay of Vcc that selects and, it would seem, ultimately corrupts the BBRAM. Oh, this is that first experiment you conducted I assume. I always wanted to hear more details about that (and, I would like you to ask you to try a couple of things, if you want to go back to this case). But, first, you say that you "observed MCU activity during RESET asserted", does this mean that you had tied up a scope both to RESET and some of the RAM signals (say, the most interesting, /CS and/or /WE), and/or VCC; and recorded this activity? Any pictures, perhaps? I stumbled onto this by happenstance and that is what piqued my interest. I took no pictures, but I used a logic analyzer, and, next time, there probably will be some. Richard Erlacher said: Not down at 2V; but that's not the point anyway. The point is, that when the voltage drops, you might have clocks missed (and the processor itself going crazy in any "funny" way), but once a certain path is blocked by a simple AND gate with one input tied directly to the RESET input, the output of the AND gate is predictible at ANY VCC.CMOS is slow, but even the old 1970's 4000-series CMOS would support a 12 MHz crystal oscillator. As you've probably gathered by now, I'm not so interested in what happens in the region approaching Vcc=2V, but, rather, more interested in what happens with 5.5V>Vcc>3.6 volts. Richard Erlacher said:
Well, unfortunately, during Vcc decay, those pump cap's are already fully charged and ready to go. As I've often pointed out, a big part of the RESET weakness is that Vcc decays too slowly. It's trivial to discharge the pumps or block their output once RESET is asserted. I'd be very surprised if the manufacturers don't do so. I should think that nothing the manfacturers fail to do would surprise you by now. ---
There is one more gotcha associated with the RESET problem, which was not discussed here so far; namely the undocumented "factory" modes of operation. Many of them work while RESET is asserted, others start to work based on a particular combination of signals at the moment when RESET is deasserted (have you seen appnotes or erratas stating "don't load /PSEN or /ALE capacitively to hard"?) It is of course next to impossible to estimate how these may or may not cause or influence the "RESET problem", as the manufacturers are completely reluctant to shed any light on the matter - and I have no time nor money to buy the equpment for reverse engineering of this extent, although, believe me, I would be very happy to do so. Well, there is that "ONCE" mode ... Also, I am aware, that we will never reach a definitive conclusion on the topic, which would make you perfectly happy and others perfectly safe. For this, the manufacturers' cooperation would be required; and, I can imagine the laughter in Atmel/NXP/wherever, when I'd go there and demand them to tell me what happens with their micro when I subject it to some extreme wiggling of VCC or whatever.
Please note, that based on the datasheets, you are not entitled to power up the circuit at all, as, taking it strictly, there is no guarantee in the datasheets it won't get damaged while VCC is below VCCmin. Another fine example of datasheet manipulation. Perhaps my suggestion that we should switch Vcc on once we KNOW it's at a valid level, and OFF when we know it's not, is not so far off. Sinking Vcc within a microsecond might not be a bad idea either. Once one's done that, a normal power-on-reset with an appropriately short rise time on Vcc would be good thing. JW
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