| ??? 05/14/06 16:55 Read: times |
#116184 - yes i had that in mind but... Responding to: ???'s previous message |
I assumed that the value becomes overwritten when using the MOVC A,@A+DPTR instruction next time as DPH will be put on P2 as well.
Mainly because CODE and XRAM share the same bus according to my knowledge. I already found one thing. I can leave the second register out, due to my stupidity it counted wrong and it works as planned if run right. |
| Topic | Author | Date |
| interrupt table copy | 01/01/70 00:00 | |
| optimisation | 01/01/70 00:00 | |
| yes i had that in mind but... | 01/01/70 00:00 | |
| No P2 worries | 01/01/70 00:00 | |
| thanks for making this clear! | 01/01/70 00:00 | |
| single chip solutions | 01/01/70 00:00 | |
| Ofcourse | 01/01/70 00:00 | |
| Why does it need optimising? | 01/01/70 00:00 | |
| Not necessarily! | 01/01/70 00:00 | |
| are you sure this is OK? | 01/01/70 00:00 | |
| THANKS! | 01/01/70 00:00 | |
| >256 byte long table | 01/01/70 00:00 | |
| I'll give it a go... | 01/01/70 00:00 | |
| worked! | 01/01/70 00:00 | |
| Re: >256 byte long table | 01/01/70 00:00 | |
| not quite this issue | 01/01/70 00:00 | |
issue resolved | 01/01/70 00:00 |