| ??? 04/14/06 06:19 Read: times |
#114286 - it would not be so simple Responding to: ???'s previous message |
hi,
Reading about hardware of 'classic' 8051 you may notice words "machine cycle", "state" and "phase". Here is from Atmel hardware manual: A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a Phase 1 half, during which the Phase 1 clock is active, and a Phase 2 half, during which the Phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (State 1, Phase 1), through S6P2 (State 6, Phase 2). Each phase lasts for one oscillator period. Each state lasts for two oscillator periods.
Typically, arithmetic and logical operations take place during Phase 1 and internal register-to-register transfers take place during Phase 2. I do stop quoting here for indicating the fact that internal hardware does recognize the each phase (read: each clock). Reading more you may find that most hardware (like UART, external data/program memory interface, port latches etc) are syncronized by phases, not by states. Valentin Angelovski said:
http://www.intel.com/design/mc...270419.htm
"There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop." I think that this is not so simple that external crystal oscillations are just divided by 2 at XTAL1 pin and then provided to rest hardware. If even so, then after divide-by-two flip-flop there is multiple-by-two circuit followed. Word "Phase"... Hmm, PLL? Regards, Oleg |
| Topic | Author | Date |
| Capacitor significance | 01/01/70 00:00 | |
| Search | 01/01/70 00:00 | |
| Why burden caps must not be omitted | 01/01/70 00:00 | |
| Thanks: But still some more | 01/01/70 00:00 | |
| because that is when the address need be | 01/01/70 00:00 | |
| Divide dy 2 | 01/01/70 00:00 | |
| Where is this divide by 2? | 01/01/70 00:00 | |
| Thank you SIR | 01/01/70 00:00 | |
| Beware of applying specifics in general! | 01/01/70 00:00 | |
| Re: clock division... | 01/01/70 00:00 | |
| I suggest you do not | 01/01/70 00:00 | |
| Misleading information | 01/01/70 00:00 | |
| Divide-by-12 = Divide-by-(2*6) | 01/01/70 00:00 | |
| Oops - 1us, not 1ms!! | 01/01/70 00:00 | |
| not exactly ... | 01/01/70 00:00 | |
| it would not be so simple | 01/01/70 00:00 | |
| Clock division - in summary | 01/01/70 00:00 | |
| Re: Clk division summary | 01/01/70 00:00 | |
| Language? | 01/01/70 00:00 | |
| ok ok one more help | 01/01/70 00:00 | |
Links | 01/01/70 00:00 |