| ??? 04/03/06 12:42 Read: times |
#113565 - because that is when the address need be Responding to: ???'s previous message |
Why is ALE generated only and always 1/6 of xtal frequency.
because that is when the address need be latched. In the few casese where that is not needed (e.g. 1 instruction byte, 2 instruction cyle execution time) who cares if ALE comes out. Why would anyone increase the complexity of a chip to avoid something that does not matter. And what is the need of internal divide dy two network when the xtal input frequecy is already divided by 12 because of its machine cycle WHAT "divide dy two network" Erik |
| Topic | Author | Date |
| Capacitor significance | 01/01/70 00:00 | |
| Search | 01/01/70 00:00 | |
| Why burden caps must not be omitted | 01/01/70 00:00 | |
| Thanks: But still some more | 01/01/70 00:00 | |
| because that is when the address need be | 01/01/70 00:00 | |
| Divide dy 2 | 01/01/70 00:00 | |
| Where is this divide by 2? | 01/01/70 00:00 | |
| Thank you SIR | 01/01/70 00:00 | |
| Beware of applying specifics in general! | 01/01/70 00:00 | |
| Re: clock division... | 01/01/70 00:00 | |
| I suggest you do not | 01/01/70 00:00 | |
| Misleading information | 01/01/70 00:00 | |
| Divide-by-12 = Divide-by-(2*6) | 01/01/70 00:00 | |
| Oops - 1us, not 1ms!! | 01/01/70 00:00 | |
| not exactly ... | 01/01/70 00:00 | |
| it would not be so simple | 01/01/70 00:00 | |
| Clock division - in summary | 01/01/70 00:00 | |
| Re: Clk division summary | 01/01/70 00:00 | |
| Language? | 01/01/70 00:00 | |
| ok ok one more help | 01/01/70 00:00 | |
Links | 01/01/70 00:00 |