| ??? 09/16/05 18:21 Modified: 09/16/05 18:22 Read: times |
#101177 - two things Responding to: ???'s previous message |
Bit banged IIC MUST be adapted to processors instruction cycle time e.g. a 2 clock LPC must have all coded delays coded 6 times longer than a "plain vanilla" running at the same clock speed. Not that you would even dream of bit-banging a LPC which has HW IIC. Likewise a difference in clock speed must be taken into consideration.
This, however, should not be an issue when the right chip is selected before starting a design. There are so many '51 derivatives today that have built-in IIC and using one of them reduces the overhead by a factor of 100. See e.g. Philips, SILabs So, use a processor that has HW IIC and put the Aspirin bottle away. Erik |
| Topic | Author | Date |
| Using IIC.ASM | 01/01/70 00:00 | |
| address, speed | 01/01/70 00:00 | |
| Yes | 01/01/70 00:00 | |
| two things | 01/01/70 00:00 | |
| Is HW I2C easier? | 01/01/70 00:00 | |
| That may have been true then, this is no | 01/01/70 00:00 | |
| Replies. | 01/01/70 00:00 | |
| Check SBCMON | 01/01/70 00:00 | |
| SBCMON | 01/01/70 00:00 | |
| try a serial memory | 01/01/70 00:00 | |
| let us try another tack | 01/01/70 00:00 | |
| another tack. | 01/01/70 00:00 | |
| you have created just about the worst co | 01/01/70 00:00 | |
| Worst conditions. | 01/01/70 00:00 | |
| oscilloscope | 01/01/70 00:00 | |
| oscilloscope | 01/01/70 00:00 | |
| To verify that your programming ("burnin | 01/01/70 00:00 | |
| verifying. | 01/01/70 00:00 | |
| Without a scope you are kind of stuck, s | 01/01/70 00:00 | |
Success. | 01/01/70 00:00 | |
| back to the roots | 01/01/70 00:00 | |
| Success. | 01/01/70 00:00 | |
| To Mike! | 01/01/70 00:00 | |
| Hello Mehdi | 01/01/70 00:00 | |
| Or... | 01/01/70 00:00 | |
| this is a bootleg, use the original | 01/01/70 00:00 | |
| i2cbits | 01/01/70 00:00 | |
| you may want to go here | 01/01/70 00:00 | |
| Clock width is only 2 uSec in IIC_ASM ex | 01/01/70 00:00 |