| ??? 06/02/13 13:03 Read: times |
#189846 - nice idea Responding to: ???'s previous message |
Hi José,
For a hobby project this is certainly a nice idea. A first step should be uploading new code. For this I think you need to be able to halt the processor. Maybe RESET is good enough for that now, but later on you'll want more I guess. I've used this method for picoBlaze cores in my design. Then you could add a SiLabs C2- or JTAG-compatible engine for programming. SiLabs has published these protocols. But the debugging part of the protocols is not published AFAIK. There are other 8051's with OCD these days but I know nothing about them. I just had a quick look at Atmel and they seem to provide quite some information about their OCD too. You state in your manual that it is impossible to VonNeumann-ize the XCODE and XDATA, but with dual-ported ram in most FPGA's this should be simple. Maarten |
| Topic | Author | Date |
| OCD for FPGA core | 01/01/70 00:00 | |
| Serial-to-EC2 reverse engineering | 01/01/70 00:00 | |
| C2spec.pdf | 01/01/70 00:00 | |
| Reality Check...... | 01/01/70 00:00 | |
| Agreed | 01/01/70 00:00 | |
| multi-threaded | 01/01/70 00:00 | |
| FPGA and soft cores | 01/01/70 00:00 | |
| Yes ... but which debugger? | 01/01/70 00:00 | |
| Actually no | 01/01/70 00:00 | |
| Who's "they" | 01/01/70 00:00 | |
| I wouldn't use FPGA unless I need more than just the core | 01/01/70 00:00 | |
| FPGA on-chip debugging redundant? | 01/01/70 00:00 | |
| debugging embedded processors | 01/01/70 00:00 | |
That's good to know. | 01/01/70 00:00 | |
| nice idea | 01/01/70 00:00 | |
| Von Neumann first | 01/01/70 00:00 | |
| if that were the case ... | 01/01/70 00:00 | |
| Poorly chosen acronym... | 01/01/70 00:00 | |
| On Chip Debug is common | 01/01/70 00:00 | |
| On Chip Debug *is* a very good idea indeed! | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 |