| ??? 06/01/13 12:12 Read: times |
#189841 - Serial-to-EC2 reverse engineering Responding to: ???'s previous message |
To reply to one of my own questions, SiLabs' serial-to-EC protocol has already been reverse engineered and a lot of info is available here: http://ec2drv.sourceforge.net/protocol.html
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| Topic | Author | Date |
| OCD for FPGA core | 01/01/70 00:00 | |
| Serial-to-EC2 reverse engineering | 01/01/70 00:00 | |
| C2spec.pdf | 01/01/70 00:00 | |
| Reality Check...... | 01/01/70 00:00 | |
| Agreed | 01/01/70 00:00 | |
| multi-threaded | 01/01/70 00:00 | |
| FPGA and soft cores | 01/01/70 00:00 | |
| Yes ... but which debugger? | 01/01/70 00:00 | |
| Actually no | 01/01/70 00:00 | |
| Who's "they" | 01/01/70 00:00 | |
| I wouldn't use FPGA unless I need more than just the core | 01/01/70 00:00 | |
| FPGA on-chip debugging redundant? | 01/01/70 00:00 | |
| debugging embedded processors | 01/01/70 00:00 | |
That's good to know. | 01/01/70 00:00 | |
| nice idea | 01/01/70 00:00 | |
| Von Neumann first | 01/01/70 00:00 | |
| if that were the case ... | 01/01/70 00:00 | |
| Poorly chosen acronym... | 01/01/70 00:00 | |
| On Chip Debug is common | 01/01/70 00:00 | |
| On Chip Debug *is* a very good idea indeed! | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 |