He's not in a hurry, but he is interested in managing noise. Fast edges will generate noise and reflections on lines longer, say, than about 3 cm. Most D-registered IC's will tolerate edges on the order of 50 ns, and perhaps more. If he clocks with 50 ns edges, by slowing his 5 ns edges down with a capacitor to Gnd and a series resistor, the receiver won't see much of the noise that would otherwise be reflected back and forth. I was looking at CMOS signals earlier that had rise and fall times on the order of 1.5 ns. I'd guess those would raise hell when fed onto a wire to a display panel.

The effects, noisewise from the digital logic signals is minuscule compared to the noise generated by the PWM switching of the LED currents.

Erik