Richard,

Your unwillingness to invest even the most minimal amount of time actually learning VHDL is apparent to all of us.



ModelSim is pretty much a gold standard of VHDL so if it doesn't understand your code, your code is at fault.

Anyways, a decimal number is also called an integer. (Or a natural, which is non-negative.) You can declare a signal as type integer and do with it what you will.

for example,

entity counter is
    port (
        clk : in std_logic;
        rst : in std_logic;
        tc : out std_logic);
end entity counter;
architecture mycounter is
     signal count : natural;
     constant TERMCNT : natural = 12345;

     TheCounter : process (clk) is
    begin
        if rising_edge(clk) then
            if (rst = '1') then
                tc <= '0';
                count <= 0;
            else
                if count = TERMCNT then
                    tc <= '1';
                    count <= 0;
                else 
                    tc <= '0';
                    count <= count + 1;
                end if;
          end if;
     end if;
end architecture  mycounter;

Or if you like, you can move the assignment to tc out of the synchronous process:

    tc <= '1' when count = TERMCOUNT else
    '0';

Now, life gets a little more difficult when going from std_logic_vectors to integers (or unsigned or signed). Why? Ask youself the following question. Given a vector "10011000", what decimal value does this represent?

-a