entity counter is
    port (
        clk : in std_logic;
        rst : in std_logic;
        tc : out std_logic);
end entity counter;
architecture mycounter is
     signal count : natural;
     constant TERMCNT : natural = 12345;

     TheCounter : process (clk) is
    begin
        if rising_edge(clk) then
            if (rst = '1') then
                tc <= '0';
                count <= 0;
            else
                if count = TERMCNT then
                    tc <= '1';
                    count <= 0;
                else 
                    tc <= '0';
                    count <= count + 1;
                end if;
          end if;
     end if;
end architecture  mycounter;