| ??? 02/03/07 00:58 Read: times |
#131945 - Fun ? Responding to: ???'s previous message |
Andy Peters said:
.... But it beats the hell out of sitting in the lab with a 'scope and a logic analyzer and constantly re-running the tools to bring test points out to FPGA pins.
Where's your sense of FUN ? Steve |
| Topic | Author | Date |
| Layout tool choice (and a bit of VHDL) | 01/01/70 00:00 | |
| Tutorials/examples in the manual | 01/01/70 00:00 | |
| Manual is informative | 01/01/70 00:00 | |
| Collars and cuffs | 01/01/70 00:00 | |
| Still runnung around | 01/01/70 00:00 | |
| If you don't own it, ... | 01/01/70 00:00 | |
Stopped working? | 01/01/70 00:00 | |
| why no "FPGA integration" | 01/01/70 00:00 | |
| clearly generic ip blocks are pretty useless | 01/01/70 00:00 | |
| Agree | 01/01/70 00:00 | |
| Fun ? | 01/01/70 00:00 | |
| Thanks for advice | 01/01/70 00:00 | |
| this is about beginning - where do you want to end | 01/01/70 00:00 | |
| It's sometimes hard to predict :) | 01/01/70 00:00 |