I am using 89v51rd2 controller. I would like to know how we can calculate the minimum interrupt latency for the controller. I am trying to read data on a data line using a clock signal line as reference with falling edge every 8 micro seconds but it is not quite working . What would be the minimum crystal requirements for this reading. It looks like I am missing interrupts .Is this feasible at all ?

For purposes of calculation let's assume you are running the v51 in 6 clock mode at 18MHz
1) the simple maximum latency is 7 instruction cycles and with the above assumption that will be ~2uS
2) an often overlooked factor in latency calculations is that the interrupt can not be serviced till servicing the same interrupt is done so you must add the processing of this ISR to the ~2uS
3) this, of course assumes that, if you have other interrupts, this is set as the only one at the highest priority.

Erik