I've looked at a few of these, but I have to say that my confidence is relatively low.

One thing I found is that the cores I've looked over seem to be very large when realized, and disproportionately slow when compared to the technology in which they're implemented.

I found it interesting that the original author of the T51 (an 805x core that was actually implemented and tested in XILINX' Spartan-II technology) operated at 16 MHz by the author's claim, yet your modification of it allowed it to run at 80 MHz. I haven't had time to study the diff's yet, but I found the T51 entirely too large.

Design of complex ALU's in the low-cost FPGA architectures is very tricky due to the small LUT's, which require they be concatenated to produce any complex function. Routing delays alone make really fast (<<10 ns) cycles through the ALU unlikely.

Asynchronism within the MCU's peripherals makes it even more difficult, particularly with respect to interrupt generation and SFR bit updates, all of which apparently hasn't slipped by your notice.

I have concluded that many of these open-sourced IP's are just trolls for consulting work. Perhaps they're useful in that respect.

RE