| ??? 12/07/10 17:42 Read: times |
#179967 - Often three layers of enable Responding to: ???'s previous message |
Note that for many ARM, you actually have three different levels of interrupt activation.
1) The specific devices. 2) The interrupt channels in the VIC. 3) The interrupt enable/disable for IRQ/FIQ in the processor core. |
| Topic | Author | Date |
| [ARM] Default state of interrupts | 01/01/70 00:00 | |
| Normally vectorized interrupt controller | 01/01/70 00:00 | |
| but isn't this the case with ALL microcontrollers? | 01/01/70 00:00 | |
| Often three layers of enable | 01/01/70 00:00 | |
| This is the case here (LPC17xx)... | 01/01/70 00:00 | |
| May vary a lot | 01/01/70 00:00 | |
| Not the case anymore for Cortex-M3s. | 01/01/70 00:00 | |
| Startup code? | 01/01/70 00:00 | |
| not startup code, but the after-reset state | 01/01/70 00:00 | |
| Hw-acceleration | 01/01/70 00:00 | |
| According to the datasheet of my CM3 ... | 01/01/70 00:00 | |
... but if we dig deeper to the datasheets... | 01/01/70 00:00 |