ts always a bad idea to use bidirectional busses internaly to a design.Its much better to have two seperate busses and to merge them together at a higher level.

o in terms of vhdl you would have :-

entity counter_load is

port ( bf_in : in std_logic_vector(7 downto 0); -- data bus in
       bf_out: out std_logic_vector(7 downto 0); -- data bus out
       ctr0_rw: in std_logic;
          .
          .
          .
)end counter_load

As you are trying to load a 16 bit value into an 8 bit bus you need to split it over two phases.Something like

        if rising edge(clk)  then
         if ctr0_RW='1' then
             if done='0' then

                if high_byte_flag='0' then
                        bf_out<=OLm;
                        high_byte_flag<='1';     --we know weve sent the high byte
                else
                        bf_out<=OLl;
                        high_byte_flag<='0';
                        done<='1';              --transfer is finished
                end if;
         else
                        done<='0';              --reset transfer flag

         end if;

        end if;