| ??? 09/06/06 07:36 Read: times |
#123727 - RISC? Responding to: ???'s previous message |
RISC means more than few instructions. Any CPU understanding such "powerful" instructions is truly CISC.
RISC mainly means: - small and efficient instruction set - very simple instructions (basic ALU ops, register transfer) - each instruction takes 1 clock cycle - few simple addressing modes (register, register indirect and immediate) - large register set - ALU operations only working with registers (socalled register-register architecture) |
| Topic | Author | Date |
| motorola versus 8051 | 01/01/70 00:00 | |
| Nebulous question | 01/01/70 00:00 | |
| all | 01/01/70 00:00 | |
| Wile E. Coyote | 01/01/70 00:00 | |
| It's not a 65HC11! It's 68HC11! | 01/01/70 00:00 | |
| ergo... | 01/01/70 00:00 | |
| QED | 01/01/70 00:00 | |
| QED ?? | 01/01/70 00:00 | |
| Q.E.D. | 01/01/70 00:00 | |
| QEF | 01/01/70 00:00 | |
| Maarten has got it right | 01/01/70 00:00 | |
| Latin... and I thought this was an english forum | 01/01/70 00:00 | |
| You've got to expand your horizons. | 01/01/70 00:00 | |
| No way... I\'m going to be in missery... | 01/01/70 00:00 | |
| Latin is more useful than C? | 01/01/70 00:00 | |
| QED | 01/01/70 00:00 | |
| QED v Q.E.D. | 01/01/70 00:00 | |
| MIPS? | 01/01/70 00:00 | |
| Processing power | 01/01/70 00:00 | |
| instruction set | 01/01/70 00:00 | |
| Architecture and Instruction Set | 01/01/70 00:00 | |
| not really | 01/01/70 00:00 | |
| It does depend on the instruction set. | 01/01/70 00:00 | |
| RISC? | 01/01/70 00:00 | |
| RISC! | 01/01/70 00:00 | |
| one instr. / cycle | 01/01/70 00:00 | |
| multiple instrcutions per cycle | 01/01/70 00:00 | |
None of this stops the mfg from calling it a RISC | 01/01/70 00:00 |