| ??? 03/04/06 22:02 Read: times |
#111267 - However with altera tools Responding to: ???'s previous message |
What you do is you set the compiler to produce a post place and route netlist which is a simulation model of the placed fpga which has an extention of vho,is basically vhdl albeit machine written and only uses the standard ieee_1164 libraries |
| Topic | Author | Date |
| Atera FPGAs | 01/01/70 00:00 | |
| Correction | 01/01/70 00:00 | |
| Careful, now ... | 01/01/70 00:00 | |
| modelsim is fine for altera fpgas | 01/01/70 00:00 | |
| Maybe, but probably not for these parts | 01/01/70 00:00 | |
| you use it seperatly | 01/01/70 00:00 | |
| aye, there's the rub ... | 01/01/70 00:00 | |
| However with altera tools | 01/01/70 00:00 | |
| Have you tried that? | 01/01/70 00:00 | |
| yep just done it now with baseline | 01/01/70 00:00 | |
| re: the rub | 01/01/70 00:00 | |
| Altera EPLDs | 01/01/70 00:00 | |
| not exactly | 01/01/70 00:00 | |
| re: not exactly | 01/01/70 00:00 | |
| Maybe you can show me ... | 01/01/70 00:00 | |
| FPGA thoughts | 01/01/70 00:00 | |
We all have thoughts... | 01/01/70 00:00 | |
| Maxplus or Quartus | 01/01/70 00:00 | |
| Do they have free simulation? | 01/01/70 00:00 | |
| Programmer | 01/01/70 00:00 | |
| Altera free simulator | 01/01/70 00:00 |