| ??? 04/18/05 12:21 Read: times |
#91817 - How true,,,,,Or Responding to: ???'s previous message |
Or getting false clocking on a signal to a serial LED driver becasue the pullup on the open drain line ends up making the signal rise time too long.
Michael Karas |
| Topic | Author | Date |
| FPGA 8051 | 01/01/70 00:00 | |
| Level translator | 01/01/70 00:00 | |
| 5V and 3.3V | 01/01/70 00:00 | |
| Read this | 01/01/70 00:00 | |
| Something else to read | 01/01/70 00:00 | |
| why and how | 01/01/70 00:00 | |
| How true,,,,,Or | 01/01/70 00:00 | |
| Surface mount :( I need DIP | 01/01/70 00:00 | |
| FPGA on perfboard?! | 01/01/70 00:00 | |
| 8051 + FPGA + OV6620 Camera | 01/01/70 00:00 | |
| My cat says....... | 01/01/70 00:00 | |
| Doh! | 01/01/70 00:00 | |
| as Andy said | 01/01/70 00:00 | |
| 8051 + FPGA + OV6620 Camera | 01/01/70 00:00 | |
| Which still begs the question.. | 01/01/70 00:00 | |
| ... and another question | 01/01/70 00:00 | |
I would | 01/01/70 00:00 | |
| I thought | 01/01/70 00:00 |