Yes steve was right:)I got all confused and friday-itis is my excuse.
Anyway here you go something which does what you want i think.You just write the multiplicand bytes to the lower and upper registers and then read the result from the three result regiters.I havent had much time to test it fully but it looks ok i would test it more but I am needed down the pub.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity mult is

 port(

            clk         : in    std_logic;
            reset       : in    std_logic;
            addr_data   : inout std_logic_vector(7 downto 0);
            addr_high   : in   std_logic_vector(7 downto 0);
            ale         : in    std_logic;
            psen_n      : in    std_logic;
            rd_n        : in    std_logic;
            wr_n        : in    std_logic

           );

end mult;

architecture rtl of mult is


type UC_STATE_TYPE is (IDLE, ADDR_DECODE,ADDR_MATCH,END_CYCLE);
signal prs_state, next_state : UC_STATE_TYPE;
signal mult_low,mult_high,addr_data_int,reg_addr : std_logic_vector(7 downto 0);
signal result : signed(19 downto 0);
signal multiplier :signed(9 downto 0);
signal ale_i,psen_i,wr_i,rd_i,uc_data_oe :std_logic;


constant upper_addr :std_logic_vector:=X"FF";   ---register addresses
constant mult_low_addr   :std_logic_vector:=X"00";
constant mult_high_addr  :std_logic_vector:=X"01";
constant result_1_addr   :std_logic_vector:=X"02";
constant result_2_addr   :std_logic_vector:=X"03";
constant result_3_addr   :std_logic_vector:=X"04";

alias result_byte_1 :signed(7 downto 0) is result(7 downto 0);
alias result_byte_2 :signed(7 downto 0) is result(15 downto 8);
alias result_byte_3 :signed(3 downto 0) is result(19 downto 16);


begin


multiplier <=signed(mult_high(1 downto 0) & mult_low);
result<= multiplier*multiplier;
addr_data<=addr_data_int when (uc_data_oe='1') else (others=>'Z');


sync:process(clk)
begin
        if rising_edge(clk) then
                ale_i<=ale;
                psen_i<=psen_n;
                rd_i<=rd_n;
                wr_i<=wr_n;

        end if;
end process;



UC_REGS: process (clk)
begin

        if rising_edge(clk) then
                if reset = '1' then
                    prs_state <= IDLE;
                else
                    prs_state <= next_state;
                end if;

        end if;

end process;


Uc_decode: process (ale_i,wr_i,rd_i)

begin
uc_data_oe<='0';
        case prs_state is
        when IDLE =>

                if ale_i='1' and psen_i = '1' then
                next_state <= ADDR_DECODE;
                end if;

        when ADDR_DECODE =>
                if ale_i='0' then
                        if (addr_high=upper_addr) then
                                if (addr_data=mult_low_addr or addr_data=mult_high_addr or addr_data=result_1_addr or addr_data=result_2_addr or addr_data=result_3_addr) then
                                                reg_addr<=addr_data;
                                                next_state<=addr_match;
                                else next_state <=idle;
                                end if;
                        end if;
                end if;

        when ADDR_MATCH =>

                if wr_i='0' then
                        case reg_addr is
                        when mult_low_addr=>mult_low<=addr_data;
                        when mult_high_addr=>mult_high<=addr_data;
                        when others =>null;
                        end case;


                elsif rd_i='0' then
                        uc_data_oe<='1';

                                case reg_addr is
                                when result_1_addr=>addr_data_int<=std_logic_vector(result_byte_1);
                                when result_2_addr=>addr_data_int<=std_logic_vector(result_byte_2);
                                when result_3_addr=>addr_data_int<=std_logic_vector("0000" & result_byte_3);
                                when others =>null;
                                end case;
                elsif rd_i = '1' and wr_i = '1' then
                                next_state <= END_CYCLE;

                end if;

        when END_CYCLE =>

        if ale_i = '0' then
        next_state <= IDLE;
        end if;


        end case;

end process;

    end rtl;

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