Sanity check needed.

I am currently using the MAX 7301 SPI I/O expander in a new project
http://pdfserv.maxim-ic.com/en/ds/MAX7301.pdf

Nice, standard SPI interface. My problem is with bit order ! I have convinced myself both ways round from the datasheet.

The datasheet says.....to WRITE to a port....

1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN—D15 first, D0 last—
observing the setup and hold times (bit D15 is low,
indicating a write command).
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low).
5) Take SCLK low (if not already low).


...and to READ from it....


Any register data within the MAX7301 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low (this enables the internal 16-bit Shift
register).
3) Clock 16 bits of data into DIN—D15 first to D0 last.
D15 is high, indicating a read command and bits
D14 through D8 containing the address of the register
to be read. Bits D7–D0 contain dummy data,
which is discarded.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low), positions D7 through D0 in the Shift register
are now loaded with the register data addressed by
bits D1 through D8.
5) Take SCLK low (if not already low).
6) Issue another read or write command (which can
be a No-Op), and examine the bit stream at DOUT;
the second 8 bits are the contents of the register
addressed by bits D1 through D8 in step 3.

Now, I am asking to read from register $40 - I can do that, and I SHOULD as far as I can see see port data from port bits 4,5,6,7 appear in D0,D1,D2,D3, with D4..D7 being 0....

NOWHERE do I get the impression that the bit order is reversed from natural order from the datasheet, except that, by examination of the bit stream it bloody well is.

AFAIK, the bit stream coming OUT of Dout is eventually (15.5 clocks late) a shifted copy of the INPUT stream, except in the reading of registers phase, the data to be transmitted is put into D7..D0.....

The code snippet in question is here.
regname is the address of the register to be read/written to.
regdataoutput is data to be transmitted to the 7301 ports
regdatainput is the address of the location for data to be received from 7301.

&MAX7301INPUT:
&Max7301OUTPUT:

	PUSH 	IE			;Save current interrupt state.
        CLR	EA
	MOV	A,max7301output|regname
	
	JB	acc.7,Readdata  ; D7 :If HIGH its a READ if LOW its a write.

 	CALL 	writedata        
        SETB	7301_cs

	POP	IE		;Don't forget interrupt on stack
	RET
	REGEND

READDATA:
	CALL 	writedata		;Write out address of register to be read, with D15 set, write 8 other bits of crap.
	SETB	7301_CS	;Then writeout dummys and read BACK from Dout
        ;Get data from chip, do 8 dummy reads and clock out the state of Dout to a register.
	CLR	7301_CS

	MOV	r0,#8
	CLR	A
	CLR 	7301_Dat		;Effectively write NOP TO selected register while still being READ
	CLR	C
loop2:	SETB	7301_Sclk
	CLR 	7301_Sclk	
	DJNZ	r0,loop2 ;This is the dummy write of first 8 bits
	
	MOV	r0,#8                   
loop3:	SETB	7301_Sclk
	MOV	C,7301_Dout
	
        CLR	7301_Sclk	
	RLC	A
	DJNZ	r0,loop3
        MOV	r0,max7301Input|regdatainput ; Get address of    register to return value of
	MOV	@r0,A           ;Result in Acc., send to indirect  
	SETB	7301_cs
	POP 	IE		;Don't forget that interrupt
	RET
	REGEND

;write out data
writedata:
	CLR 	7301_sclk
        CLR 	7301_CS
        CALL    clockdata ;Acc contains address of internal                    register to set
        MOV	A,max7301output|regdataoutput  ; Now acc contains data to set.
        CALL 	clockdata
        SETB	7301_CS
        RET

clockdata:
	MOV 	r0,#8
loop1:  RLC 	A
	MOV 	7301_dat,C
        SETB	7301_sclk
        clr     7301_sclk
        DJNZ 	r0,loop1
        RET  

The weird thing is, everything works, I can read and write, but the bit order in the readback seems reversed. What have I missed. D15..D0 come trotting out of Dout, I capture the last 8 bits, and as they arrive clock them LEFT into the accumulator, so that d7 is in the left most place and D0 is in the right most place....

But this ISN'T how it looks. If I change the RLC in loop3 to RRC the bit order is correct, as per the datasheet, but not as per my view of the bitstream.

WHERES THE ERROR !

Steve