I have always used non volatile SRAM in my processor designs, but in my quest for more power I have been forced to look at standard SRAM and a Non volatile controller with battery backup. It was no problem to remove a RAM from a project and drop it into another development system to be programmed as it would retain it's memory. But now, I cannot remove the SRAM or the contents will be lost, so I have to come up with a way to have memory access whilt the SRAM is still under full power in it's socket...I thought one way would be to fully buffer the address and data busses, then with the 3state enable, I could effectively "disconnect" the processor leaving the SRAM free for another processor to have access to, but this will add 4 chips to the design...is there an easier way to do this?? I also thought about putting the processor into a semi-permanent state of reset, but I'm not sure if the port pins have a strong pullup or a weak one.....Any suggestions would be greatly appreciated...

Thanks....