Here's some code to read the mag device and xor combine the dibits into 5bit bytes, appended into a 40 byte buffer. It does everything but check the parity bit of the byte bytes of data but that could be done once the mag card is read and you're validating the buffer with plenty of time.

This browser email messes up the format of the code, but its here below. Let me know if you want a cleaner copy emailed directly to you.

-Jay C. Box

;---------------;
bseg
b_mag: dbit 1 ;phase flag
b_bfr: dbit 1 ;buffer complete
;---------------;
iseg
i_bfr ds 40 ;mag buffer
;---------------;
cseg
reg_run equ 00000000b ;set 0 fo foreground
reg_mag equ 00001000b ;set 1 for mag task
MAGPORT equ (input bit)
;---------------;
org 00003h
v_int0:
clr ie0 ;2;12 ;clr ntr flag
ajmp ntr_mag ;2;24 ;go
;---------------;
org (elsewhere)
ntr_mag:
jb b_bfr,not_mag ;3;24 ;qik out if buffer full
push psw ;2;24
push acc ;2;24
mov psw,reg_mag ;3;24 ;load reserved reg set
mov c,MAGPORT ;2;12 ;read bit at t=~12us+ <------
clr a ;1;12 ;need clr for sev reasons
rlc a ;1;12 ;mov to acc.0
cpl b_mag ;2;12 ;toggle phase bit
jnb b_mag,ntr_mag2 ;3;24 ;jif phase 2 else phase 1
mov r7,a ;1;12 ;sav 1st bit of dibit in r7.0
xit_mag:
pop acc ;2;24
pop psw ;2;24
not_mag:
reti ;1;24
ntr_mag2:
xrl a,r7 ;1;12 ;combine dibits for true bit
rrc a ;1;12 ;move result into cy
mov a,r6 ;1;12 ;get byte-builder
rlc a ;1;12 ;shf bit into acc.0
mov r6,a ;1;12 ;sav
djnz r2,xit_mag ;2;24 ;xif not 5 bits yet
mov r2,#5 ;2;12 ;init for next 5 bits
mov @r1,a ;1;12 ;put in bfr
inc r1 ;1;12 ;bump
djnz r3,xit_mag ;2;24 ;xif not 40 bytes in buffer
mov r3,#40 ;2;24 ;ini for nxt 40 bytes
clr b_mag ;2;12 ;phase bit to known state
setb b_bfr ;2;12 ;signal foreground buffer full
ajmp xit_mag ;2;24 ;bail
;---------------;
ini_mag: ;foreground initialization
push psw ;2;24
mov psw,reg_mag ;3;24
mov r7,#0 ;2;12 ;byte builder
mov r6,#i_bfr ;2;12 ;pointer into buffer
mov r2,#5 ;2;12 ;5 bit counter
mov r3,#40 ;2;12 ;40 byte counter
clr b_mag ;2;12 ;dibit phase1
clr b_bfr ;2;12 ;mag bfr avail
pop psw
ret
;---------------;