Matthew,

You should read carefully the PSD module description in the datasheet. I know it is rather confusing, but try to go through it a couple of times.

What you have there is in fact an integrated version of what used to be on a high-end board a decade or two ago: eight FLASH chips (the main FLASH memory comprising of eight sectors), four more FLASH chips (the secondary FLASH memory with four sectors), a SRAM chip and a bunch of I/Os, but we are not going to deal with these now. They all share a common data memory and an address memory. However, to determine which chip will receive and output data onto the data bus, all of these have a pin called chip select, and these pins are fed from a so called address decoder, which is usually just a set of gates driven from the highest address bits, and determines which chip select will be active for which combination of zeros and ones on the highest address bits. For example, if there is an AND gate with inputs tied to A15 and A14 and its output to (active low) chip select of the first FLASH chip, this FLASH chip would output data in the range of addresses 0000-3FFF.

There can be more inputs to the address decoder: read and write signals (and /psen in case of '51), so that different memories can be mapped on the same address for read, write and code fetch. And, to facilitate big memories, which inevitable need to be mapped to the same address range, outputs of a paging register (which is a multi-bit latch writable from the processor or mcu). Thus, writing a certain value to this register would change behaviour of the address register, enabling one memory for one value of page register, and another for another value of the address register.

You have all these constituents in the PSD part of the uPSD, and the address decoder is in form of a PLD, programmable together with the FLASH via JTAG. You have a page register there, and it is this page register you use to determine which sector of the FLASH will be active at which time. The software for uPSD configuration (PSDSoft or CUPS, I don't know the latter as it was quite a time I used the PSD/uPSDs the last time) will guide you to set up the content and behaviour of decode PLD (the address decoder). The page register is part of the CSIOP area, so you access it in a similar way as you access the PSD ports and other registers.

Feel free to ask, but given me forgetting a lot of things I don't guarantee to answer...

JW