| ??? 08/19/07 14:50 Read: times |
#143399 - Designing a pre-test environment ... Responding to: ???'s previous message |
Jan,
I'm gradually setting up an experiment that uses two of the Dallas BBRAM types, one, a DS1230Y and the other, a Dallas "smart socket" with a standard 32Kx8 SRAM. I could use a pair of the DS1230's, but since I've had some BBRAM corruption in the presence of both of these, I probably will want to stick with them for purpose of this exercise. I can control the rise time of Vcc and its fall time, as I'm driving Vcc from an emitter follower controlled by a pulse generator that allows me to control the rise and fall times separately. I'll be using a mosfet, optionally, to discharge Vcc quite precipitously on command. I'm also contemplating a means for stopping the oscillator during the first part of the assertion of RESET so that Vcc can drop below 0.7 volts, and then rise again. Hopefully all the available options can be explored in this circuit. There are some other options I want to be able to consider as well, such as automatically checking the BBRAM content, and monitoring the BBRAM controls during the critical period during which the control signals are falling, along with Vcc, through that range in which Vcc is low but seemingly not low enough to prevent MCU misbehavior or independent BBRAM malfunction, whichever the case may be. I'm not sure exactly how this will work, hence, I'm not yet ready to implement such a circuit. Ultimately, I expect I'll also be able to use the same setup to perform a long-term test of the RESET behavior of various 805x-core MCU's. My first effort will be simply to monitor the behavior of the 805x/BBRAM interaction during the fall of Vcc, with a ~250 microsecond rise time of Vcc. My goal, for now, is to establish what each involved MCU requires in order to attain normal operation. I expect I'll use the unpopular RC reset at the beginning, but will provide a supervisor in order to make a comparison of the behavior. Remember, I'm not opposed to the use of supervisors, but I am curious whether they do anything at all to mitigate the risk of system malfunction during the power-down transient. If you have any specific suggestions as to the stimulation or monitoring of the circuit, referenced to specific signals, I'd be happy to take them into consideration. RE |



