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???
08/19/07 14:50
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#143399 - Designing a pre-test environment ...
Responding to: ???'s previous message
Jan,

I'm gradually setting up an experiment that uses two of the Dallas BBRAM types, one, a DS1230Y and the other, a Dallas "smart socket" with a standard 32Kx8 SRAM. I could use a pair of the DS1230's, but since I've had some BBRAM corruption in the presence of both of these, I probably will want to stick with them for purpose of this exercise.

I can control the rise time of Vcc and its fall time, as I'm driving Vcc from an emitter follower controlled by a pulse generator that allows me to control the rise and fall times separately. I'll be using a mosfet, optionally, to discharge Vcc quite precipitously on command. I'm also contemplating a means for stopping the oscillator during the first part of the assertion of RESET so that Vcc can drop below 0.7 volts, and then rise again. Hopefully all the available options can be explored in this circuit.

There are some other options I want to be able to consider as well, such as automatically checking the BBRAM content, and monitoring the BBRAM controls during the critical period during which the control signals are falling, along with Vcc, through that range in which Vcc is low but seemingly not low enough to prevent MCU misbehavior or independent BBRAM malfunction, whichever the case may be.

I'm not sure exactly how this will work, hence, I'm not yet ready to implement such a circuit. Ultimately, I expect I'll also be able to use the same setup to perform a long-term test of the RESET behavior of various 805x-core MCU's.

My first effort will be simply to monitor the behavior of the 805x/BBRAM interaction during the fall of Vcc, with a ~250 microsecond rise time of Vcc. My goal, for now, is to establish what each involved MCU requires in order to attain normal operation. I expect I'll use the unpopular RC reset at the beginning, but will provide a supervisor in order to make a comparison of the behavior.

Remember, I'm not opposed to the use of supervisors, but I am curious whether they do anything at all to mitigate the risk of system malfunction during the power-down transient.

If you have any specific suggestions as to the stimulation or monitoring of the circuit, referenced to specific signals, I'd be happy to take them into consideration.

RE


List of 39 messages in thread
TopicAuthorDate
the mysterious data loss in BBRAM            01/01/70 00:00      
   I just used the Dallas parts!            01/01/70 00:00      
      I've heard only praises to the Dallas chips, too..            01/01/70 00:00      
         I agree re Dallas            01/01/70 00:00      
            another method            01/01/70 00:00      
               I don't understand            01/01/70 00:00      
                  nah            01/01/70 00:00      
                     ... I just would expect that..            01/01/70 00:00      
                        You are absolutely right, of course!            01/01/70 00:00      
                     You should dig deep when posting here!            01/01/70 00:00      
                        nope, but ...            01/01/70 00:00      
                           But, what if your post is just wrong??            01/01/70 00:00      
                              well, it was not            01/01/70 00:00      
                                 What has this to do with Jan's application??            01/01/70 00:00      
                                    everything            01/01/70 00:00      
                                       When you use a second supervisor chip, ...            01/01/70 00:00      
                                          it does - IF            01/01/70 00:00      
                                             For occasional writes you have the FLASH            01/01/70 00:00      
                                                this depends on application, too            01/01/70 00:00      
                                                   But why??            01/01/70 00:00      
                                                      early power fail interrupt .....            01/01/70 00:00      
                                                         this is the purpose of reset            01/01/70 00:00      
                                                            Sadly, there's no guarantee it does that!            01/01/70 00:00      
                                                               ensure the same voltage on mcu and RAM/supervis            01/01/70 00:00      
                                                               yeah, sure            01/01/70 00:00      
                                                            OK, once more            01/01/70 00:00      
                                                               given a proper ground and power plane ...            01/01/70 00:00      
                                                         I have to agree ...            01/01/70 00:00      
                                             this depends on application            01/01/70 00:00      
                                             There's room for doubt ...            01/01/70 00:00      
                                       thanks            01/01/70 00:00      
                                 sounds reasonably            01/01/70 00:00      
   Pull-downs at inputs of battery powered CMOS-RAM            01/01/70 00:00      
      Observation technique affects the outcome            01/01/70 00:00      
         Some comments and two questions            01/01/70 00:00      
   Designing a pre-test environment ...            01/01/70 00:00      
      Eager to hear the results!            01/01/70 00:00      
         You'll have to be patient ...            01/01/70 00:00      
   Has anyone tried THIS?            01/01/70 00:00      

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