Hello Group,
I am using I2c protocol for the interface between my AT89S52 microcontroller and an I2C compatible EEPROM.

Now as far as my understanding of the protocol goes, there are two operational speeds - 100KHz and 400KHz.

For operating at 100KHz, is it essential to provide a 50% duty cycle (5 uSec - 5 uSec)on the clock line (SCL) once the start condition is met,ie both HIGH and LOW clock periods are of duration 5 uSec.

Or can i transfer data with ny time duration of the low and high clock pulses which remain constant as the cycle repeats itself,ie the time period of the LOW and HIGH periods vary for
every bit of data that is to be transmitted/received.

Is the I2C compatible EEPROM fine tuned to receive/tarnsmit data bits at 50% duty cycle of clock only ?

Thanks and Regards
Manish Gajjaria