| ??? 09/29/05 16:41 Read: times |
#101731 - Ok... I follow you, but... Responding to: ???'s previous message |
Probably not enough coffee. Both /PSEN and /RD are active LOW (and so are the control signals (/CS, /OE, /WE) of almost all memories). AND is in fact OR for negative logic. I switch to tea after 10am... ;) Ok... I checked a datasheet, and you're right /RD is not asserted for program store read, just /PSEN. I follow you so far, but we probably still need a schematic from Brice to figure out where the problem is. |
| Topic | Author | Date |
| Buffering address/data bus Basic-52 | 01/01/70 00:00 | |
| direction | 01/01/70 00:00 | |
| Yes | 01/01/70 00:00 | |
| '573? | 01/01/70 00:00 | |
| 245 | 01/01/70 00:00 | |
| Only need one latch | 01/01/70 00:00 | |
| Re-read this... | 01/01/70 00:00 | |
| negative logic | 01/01/70 00:00 | |
| caqll a spade a spade | 01/01/70 00:00 | |
| Ok... I follow you, but... | 01/01/70 00:00 | |
| 74F623 instead of 74F245 | 01/01/70 00:00 | |
| I'd stick with a 245 | 01/01/70 00:00 | |
74AC623 is also fast | 01/01/70 00:00 | |
| A little clarification | 01/01/70 00:00 | |
| if you are ANDing them it will never wor | 01/01/70 00:00 | |
| How fast is your memory? | 01/01/70 00:00 |