| ??? 09/28/05 16:21 Read: times |
#101678 - then this is a bad title. Responding to: ???'s previous message |
i've concerned master/slave. the idea is to connect more or less 1 master and 6 slaves
then this is a bad title. with (pre) and (/pre) not used your code is unreadable, so I will give a few pointers instead. 1) look at the turning of the bus at both nodes. 2) if you are not using 3 resistor termination DO IT NOW. 3) if you are using chips with node recognition SFRs make sure they are set right. 4) before doing ANYTHING else, do a debug of unidirectionl code both ways (comment code out to make uC a recieve all the time and uC b transmit all the time, when that works reverse and make that work THEN, and only then, get into direction switching). Erik |
| Topic | Author | Date |
| Serial communication between 2 at89c52 | 01/01/70 00:00 | |
| I had a quick look and since I am not | 01/01/70 00:00 | |
| pic? | 01/01/70 00:00 | |
| again | 01/01/70 00:00 | |
| re your ISR | 01/01/70 00:00 | |
| i've modified the ISR | 01/01/70 00:00 | |
| get it going with a PC at one end that g | 01/01/70 00:00 | |
| i'll try 2 do that | 01/01/70 00:00 | |
| transmit | 01/01/70 00:00 | |
| sorry | 01/01/70 00:00 | |
| No, do it in the interrupt | 01/01/70 00:00 | |
| must be like this? | 01/01/70 00:00 | |
| should be | 01/01/70 00:00 | |
| thanks | 01/01/70 00:00 | |
| NO | 01/01/70 00:00 | |
| problems again, pls help me | 01/01/70 00:00 | |
still don't get it | 01/01/70 00:00 | |
| with only two processors why are you con | 01/01/70 00:00 | |
| i've said | 01/01/70 00:00 | |
| then this is a bad title. | 01/01/70 00:00 |