library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity pulsegen is
    Port ( clkin    : in  STD_LOGIC;
           pulseOut : out STD_LOGIC);
end pulsegen;

architecture Behavioral of pulsegen is
	COMPONENT myDCM
	PORT(
		CLKIN_IN : IN std_logic;          
		CLKFX_OUT : OUT std_logic;
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic
		);
	end component;

signal clkfxout, xxx, clk0out, cigo : std_logic;
begin
	Inst_myDCM: myDCM PORT MAP(
		CLKIN_IN => clkin,
		CLKFX_OUT => clkfxout,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => open
	);
	process (clkfxout)
		begin
			if rising_edge(clkfxout) then
				xxx <= (xxx xor '1');
			end if;
		end process;
	pulseOut <= xxx;
end Behavioral;