signal newval : signed(7 downto 0);
signal acc : signed(9 downto 0);
signal avg : signed(7 downto 0);

accumulator : process (clk) is
begin
    if rising_edge(clk) then
        if (clear = '1') then
            acc <= (others => '0'); -- it's still a bit vector
        else
            acc <= acc + resize(newval, acc'length);
        end if; -- clear
    end if; -- rising_edge
end process accumulator;