module uat
    (input wire MClk,		// master clock
     input wire BaudClk,	// clock enable at the baud rate
     input wire Strobe,		// indicates new word
     input wire [7:0]DataIn,	// new word to write
     output reg RS232Out,	// serial transmit data
     output reg TxBusy);	// transmitter is busy

    reg [9:0] 	iTxShift;	// transmit shift reg
    reg [3:0] 	iBitCnt;	// bit counter

    // Shifter loads when strobe is asserted coincident with a new word coming
    // in on DataIn, and it resets the shift and bit counters.
    // Shift takes place when BaudClk is asserted.  It should be one MClk tick
    // wide every transmit bit time.
    always @(posedge MClk) begin : Shifter
	if (Strobe) begin
	    iTxShift   <= {1'b1, DataIn, 1'b0};	// love concatenation!
	    iBitCnt    <= 9;
	    TxBusy     <= 1'b1;
	end else begin // if (Strobe)
	    if (BaudClk) begin
		if (iBitCnt != 0) begin
		    iTxShift   <= {1'b0, iTxShift[9:1]};
		    iBitCnt    <= iBitCnt - 1;
		end
		RS232Out       <= iTxShift[0];
		TxBusy 	       <= (iBitCnt != 0);
	    end // if (BaudClk)
	end // else: !if(Strobe)
    end // block: Shifter
endmodule // uat