module clockdiv
    #(parameter DIVCNT = 1000,	// count to this number
                DIVSIZE = 10)   // need enough bits to count to DIVCNT
    (input wire MClk,		// FPGA master clock
     output reg ClkDiv);	// clock divider strobe out

    reg [DIVCNT:0] iCounter; 	// our counter

    // when counter hits target DIVCNT, assert the ClkDiv strobe and
    // reset the counter.
    // Otherwise, just count and keep ClkDiv cleared.
    always @(posedge MClk) begin : Divider
	if (iCounter == DIVCNT) begin
	    ClkDiv     <= 1'b1;
	    iCounter   <= 0;
	end else begin
	    ClkDiv     <= 1'b0;
	    iCounter   <= iCounter + 1;
	end // else: !if(iCounter == DIVCNT)
    end // block: Divider
endmodule // clockdiv