module toplevel
    #(parameter DIVCNT = 1000,	// count to this number
                DIVSIZE = 10)   // need enough bits to count to DIVCNT
    (input wire MClk,		// FPGA master clock
     input wire Strobe,		// true with new data word
     input wire [7:0]DataIn,	// new word to write
     output reg RS232Out,	// serial transmit data
     output reg TxBusy);	// transmitter is busy

    // clock divider output:
    wire 	ClkDiv;
    
    // here is the clock divider:
    clockdiv 
	#(.DIVCNT(DIVCNT),
	  .DIVSIZE(DIVSIZE)) u0
	    (.MClk(MClk),
	     .ClkDiv(ClkDiv));

    // and the transmitter:
    uat u1
	(.MClk(MClk),
	 .BaudClk(BaudClk),
	 .Strobe(Strobe),
	 .DataIn(DataIn),
	 .RS232Out(RS232Out),
	 .TxBusy(TxBusy));

endmodule // toplevel