/* ////////////////////////////////////////////////////////////////////////////
                                    uat_s.v
///////////////////////////////////////////////////////////////////////////////
DESCRIPTION:    This module exercises the UAT (UART without the R) module on
                the real hardware.

REVISIONS:      29 Sep 07 - RAC - Skeleton that's just enough to get it to
                                   synthesize.
                29 Sep 07 - RAC - Added more stuff so it actually works on the
                                   eval board.
//////////////////////////////////////////////////////////////////////////// */

`timescale 1ns / 1ps

`include "../modules/mcd.h"
`include "../modules/uat.v"

/* ////////////////////////////////////////////////////////////////////////////
                                    uat_s()
///////////////////////////////////////////////////////////////////////////////
DESCRIPTION:    The highest level module.

REVISIONS:      29 Sep 07 - RAC - Genesis
//////////////////////////////////////////////////////////////////////////// */

module uat_s (clock50mhz, rs232out, baudClock, byteClock);

    input  clock50mhz;                          // Eval board's 50 MHz clock
    output rs232out;                            // TxD to a PC or something
    output baudClock;                           // 9600 Hz clock
    output byteClock;                           // 20 Hz clock

    reg [7:0]   data;

    MakeBaudClock divider1 (clock50mhz, baudClock);
    MakeByteClock divider2 (baudClock,  byteClock);
    UAT uart (baudClock, data, byteClock, rs232out);

    always @(posedge byteClock) begin
        if (data == 122) begin
            data <= 97;
            end
        else begin
            data <= data + 1;
            end
        end

    endmodule

/* ////////////////////////////////////////////////////////////////////////////
                                MakeBaudClock()
///////////////////////////////////////////////////////////////////////////////
DESCRIPTION:    THis module divides the eval board's on-board 50 MHz clock down
                to 9600 Hz for use as a baud clock.

REVISIONS:      29 Sep 07 - RAC - Adapted from previous work
//////////////////////////////////////////////////////////////////////////// */

`define MAX_COUNT       5208                    // Divide by this number
`define UP_TIME         2604                    // Set output duty cycle to 50%
`define COUNTER_WIDTH   13                      // Enough bits to hold a value
                                                //  of MAX_COUNT, but no more
                                                //  than necessary
module MakeBaudClock(in, out);
    input in;
    output out;

    reg [`COUNTER_WIDTH-1 : 0] counter;         // Count input pulses here
    reg out;                                    // Manage output signal here

    always @(posedge in) begin                  // On every input pulse
        if (counter == `MAX_COUNT - 1) begin    // Time to reset the counter
            counter <= 0;                       // Do so
            end                                 // End 'time to reset counter'
        else begin                              // Not time to reset counter
            counter <= counter + 1;             // Increment it instead
            end                                 // End 'not time to reset'
        out <= counter < `UP_TIME;              // Output is high from counter
        end                                     // End 'on every input pulse'

    endmodule

`undef MAX_COUNT
`undef UP_TIME
`undef COUNTER_WIDTH

/* ////////////////////////////////////////////////////////////////////////////
                                MakeByteClock()
///////////////////////////////////////////////////////////////////////////////
DESCRIPTION:    THis module divides the 9600 Hz baud clock down to 20 Hz for
                use as a character output clock.

REVISIONS:      29 Sep 07 - RAC - Adapted from MakeBaudClock()
//////////////////////////////////////////////////////////////////////////// */

`define MAX_COUNT       480                     // Divide by this number
`define UP_TIME         2                       // Make it a narrow pulse
`define COUNTER_WIDTH   9                       // Enough bits to hold a value
                                                //  of MAX_COUNT, but no more
                                                //  than necessary
module MakeByteClock(in, out);
    input in;
    output out;

    reg [`COUNTER_WIDTH-1 : 0] counter;         // Count input pulses here
    reg out;                                    // Manage output signal here

    always @(posedge in) begin                  // On every input pulse
        if (counter == `MAX_COUNT - 1) begin    // Time to reset the counter
            counter <= 0;                       // Do so
            end                                 // End 'time to reset counter'
        else begin                              // Not time to reset counter
            counter <= counter + 1;             // Increment it instead
            end                                 // End 'not time to reset'
        out <= counter < `UP_TIME;              // Output is high from counter
        end                                     // End 'on every input pulse'

    endmodule

`undef MAX_COUNT
`undef UP_TIME
`undef COUNTER_WIDTH