`ifdef ON_TEST_BENCH
module DivideByN(in, out, counter);
    input in;
    output out;
    output counter;
`else
module DivideByN(in, out);
    input in;
    output out;

`endif
    reg [`COUNTER_WIDTH-1 : 0] counter;		// Count input pulses here
    reg out;					// Manage output signal here
    initial begin
	counter <= 0;
	end
    always @(posedge in) begin			// On every input pulse
	if (counter == `MAX_COUNT - 1) begin	// Time to reset the counter
	    counter <= 0;			// Do so
	    end					// End 'time to reset counter'
	else begin				// Not time to reset counter
	    counter <= counter + 1;		// Increment it instead
	    end					// End 'not time to reset'
	out <= counter < `UP_TIME;		// Output is high from counter
	end					// End 'on every input pulse'
    endmodule