This is a Lite version of ISE Simulator.
Simulator is doing circuit initialization process.
Finished circuit initialization process.
counter:  0, out: x
counter:  1, out: 1
counter:  2, out: 1
counter:  3, out: 1
counter:  4, out: 0
counter:  5, out: 0
counter:  6, out: 0
counter:  7, out: 0
counter:  8, out: 0
counter:  9, out: 0
counter:  0, out: 0
counter:  1, out: 1
counter:  2, out: 1
counter:  3, out: 1
counter:  4, out: 0
counter:  5, out: 0
counter:  6, out: 0
counter:  7, out: 0
counter:  8, out: 0
counter:  9, out: 0
counter:  0, out: 0
counter:  1, out: 1
counter:  2, out: 1
counter:  3, out: 1
counter:  4, out: 0
counter:  5, out: 0
counter:  6, out: 0
counter:  7, out: 0
counter:  8, out: 0
counter:  9, out: 0
Stopped at time : 60.000 ns : File "C:/verilog/a/dbn_t.v" Line 23