always @(posedge clock50Mhz or negedge rst_l) begin
	if (~rst_l) begin
	    clockDividerNB  <= 0;
	    outputBitNB	    <= 1'b0;
	end else begin	    
	    if (clockDividerNB == 49999) begin
		clockDividerNB 	 <= 0;
	    end else begin
		clockDividerNB 	 <= clockDividerNB + 1;
	    end
	    outputBitNB 	 <= (clockDividerNB < 9999) ? 1 : 0;
	end // else: !if(~rst_l)
    end // always @ (posedge clock50Mhz or negedge rst_l)