reg [15:0] clockDivider;                // A 16-bit counter
    reg outputBit;                          // 1 KHz, 20% duty cycle signal

    always @(posedge clock50Mhz) begin      // On 50 MHz clock rising edge
        clockDivider = clockDivider + 1;    // Bump the counter
        if (clockDivider == 50000) begin    // One millisecond has gone by
            clockDivider = 0;               // Reset the counter
            end                             // End 'one msec has gone by'
        outputBit =                         // Assert the output for 20%
            (clockDivider < 10000) ? 1 : 0; //  of the one ms period
        end                                 // End 'on 50MHz rising edge'