process(FCLK, RSTn)
		begin
			if(RSTn = '0') then
				shift_reg <= x"34fe";
			end if;
			if(rising_edge(FCLK)) then
				shift_reg <= shift_reg(14 downto 0) & (shift_reg(15) xor shift_reg(14) xor shift_reg(12) xor shift_reg(3));
				if(shift_reg = x"0000") then
					shift_reg <= x"f432";
				elsif(GEN = '0') then -- generate random number key
					OUTPUTS <= shift_reg;
				end if;
			end if;
	end process;