library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rand is
    Port ( FCLK    : in  STD_LOGIC;
           RSTn    : in  STD_LOGIC;
           GEN     : in  STD_LOGIC;
           OUTPUTS : out  STD_LOGIC_VECTOR (15 downto 0));
end rand;

architecture Behavioral of rand is
signal shift_reg : std_logic_vector(15 downto 0);
begin
	process(FCLK, RSTn)
		begin
			if(RSTn = '0') then
				shift_reg <= x"34fe";
			elsif(rising_edge(FCLK)) then
				shift_reg <= shift_reg(14 downto 0) & (shift_reg(15) xor shift_reg(14) xor shift_reg(12) xor shift_reg(3));
				if(shift_reg = x"0000") then
					shift_reg <= x"f432";
				elsif(GEN = '0') then -- generate random number key
					OUTPUTS <= shift_reg;
				end if;
			end if;
	end process;
end Behavioral;