addrlatch : process (ale, p0) is
begin
    latch : if (ale = '1') then
        addrlo = p0;
    end if latch;
end process addrlatch;

regwrite : process (wr_l) is
begin
    if rising_edge(wr_l) then
        isRegA : if ((p2 & addrlo) = X"8000") then
            regA <= p0;
        end if isRegA;

        isRegB : if ((p2 & addrlo) = X"A000") then
            regB <= p0;
        end if isRegB;
    end if; // rising_edge
end process regwrite;

regread : process (p2, addrlo, rd_l, regA, regB) is
begin
    if (rd_l = '0') then
        decode : case (p2 & addrlo) is
            when X"8000" =>
                ip0 <= regA;
            when X"A000" =>
                ip0 <= regB;
            when others =>
                ip0 <= X"00";
         end case decode;
    end if; // rd_l = '0'
end process regread;

p0 <= ip0 when rd_l = '0' else (others => 'Z');