entity foo is
    port (
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic;
    q_l : out std_logic);
end entity foo;

architecture bar of foo is
    signal q_i : std_logic;  -- "dummy" internal q
begin
    q   <= q_i;      -- use dummy because 
    q_l <= not q_i;  -- we can't do q_l <= not q

    flop : process (clk) is
    begin
        q_i <= d;
    end process flop;
end architecture bar;