------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity fulladder is port ( addend : in bit; augend : in bit; carry_in : in bit; sum : out bit; carry : out bit ); end fulladder; architecture data_flow of fulladder is begin sum <= ((addend xor augend) xor carry_in); carry <= ((addend and augend) or (carry_in and (addend or augend))); end data_flow;