signal count_i : unsigned (WIDTH-1 downto 0);
mycounter : process (clk, arst_l) is
begin
    if (arst_l = '0')  then  -- async reset
        count_i <= (others => '0');
    elsif rising_edge(clk)
    begin
        if (srst = '1') then -- synchronous reset
            count_i <= (others => '0');
        elsif (load = '1') -- synchronous load
            count <= unsigned(initval);
        elsif (enable  = '1') then
            if (count_i = (others => '1')  then -- gracefully handle overflow
                count_i <= (others => '0');
            else
                count_i <= count_i + 1;
            end if;
        end if; -- enable/reset/load?
    end if; -- clock edge
end process mycounter;

countout <= std_logic_vector(count_i);