-- Xilinx_counter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Xilinx_counter is
     Generic(width : integer := 3); -- behavioral counter can be any size you want simply by changing one number!
     Port(
      clock : in  STD_LOGIC;
      R     : in  STD_LOGIC;
		
      count : out  STD_LOGIC_VECTOR(width-1 downto 0)
     );
end Xilinx_counter;

architecture Behavioral of Xilinx_counter is

signal count_int : STD_LOGIC_VECTOR(width-1 downto 0);

begin

process(R, clock)
begin
     if (R = '1') then
	count_int <= (OTHERS => '0');
     elsif rising_edge(clock) then
	count_int <= count_int + '1'; -- can be an up by X counter by changing just one other number!
     end if;
end process;

count <= count_int;

end Behavioral;