sfr S0_TCON           = 0x88;    // timer control            
  sbit    SB0_TCON_IT0  = 0x88;
  sbit    SB0_TCON_IE0  = 0x89;
  sbit    SB0_TCON_IT1  = 0x8A;
  sbit    SB0_TCON_IE1  = 0x8B;
  sbit    SB0_TCON_TR0  = 0x8C;
  sbit    SB0_TCON_TF0  = 0x8D;
  sbit    SB0_TCON_TR1  = 0x8E;
  sbit    SB0_TCON_TF1  = 0x8F;
  #define SM_TCON_IT0     0x01
  #define SM_TCON_IE0     0x02
  #define SM_TCON_IT1     0x04
  #define SM_TCON_IE1     0x08
  #define SM_TCON_TR0     0x10
  #define SM_TCON_TF0     0x20
  #define SM_TCON_TR1     0x40
  #define SM_TCON_TF1     0x80


//S0_TCON = SM_TCON_IT0 + SM_TCON_IE0 + SM_TCON_IT1 + SM_TCON_IE1 + SB0_TCON_TR0 + SB0_TCON_TF0 + SB0_TCON_TR1 + SB0_TCON_TF1;
  S0_TCON = SM_TCON_IT0               + SM_TCON_IT1                                                                          ;
//S0_TMOD = SM_TMOD_T1CLR + SM_TMOD_T0TM1 + SM_TMOD_T0CM1 + SM_TMOD_T0CLR + SM_TMOD_T1TM1 + SM_TMOD_T1CM1 + SM_TMOD_T1TM2;
  S0_TMOD =                                 SM_TMOD_T0CM1                                 + SM_TMOD_T1CM1                ;