/*-----------------------------------------------------------------------------
  STC15F10.H

Header file for STC 15F10x devices.
Copyleft 2013 Mikkel C. Simonsen
No rights reserved.
-----------------------------------------------------------------------------*/

#ifndef __STC15F10_H__
#define __STC15F10_H__

/* Byte Registers */
sfr SP          = 0x81;            /*                                        */
sfr DPL         = 0x82;            /* Data Pointer Low                       */
sfr DPH         = 0x83;            /* Data Pointer High                      */
sfr PCON        = 0x87;            /*                                        */
sfr TCON        = 0x88;            /*                                        */
sfr TMOD        = 0x89;            /*                                        */
sfr TL0         = 0x8A;            /*                                        */
sfr TL1         = 0x8B;            /*                                        */
sfr TH0         = 0x8C;            /*                                        */
sfr TH1         = 0x8D;            /*                                        */
sfr AUXR        = 0x8E;            /*                                        */
sfr INT_CLKO    = 0x8F;            /*                                        */
sfr CLK_DIV     = 0x97;            /*                                        */
sfr IE          = 0xA8;            /* Interrupt Enable                       */
sfr P3          = 0xB0;            /* Port 3                                 */
sfr P3M1        = 0xB1;            /*                                        */
sfr P3M0        = 0xB2;            /*                                        */
sfr IP          = 0xB8;            /* Interrupt Priority                     */
sfr IRC_CLKO    = 0xBB;            /*                                        */
sfr WDT_CONTR   = 0xC1;            /*                                        */
sfr IAP_DATA    = 0xC2;            /*                                        */
sfr IAP_ADDRH   = 0xC3;            /*                                        */
sfr IAP_ADDRL   = 0xC4;            /*                                        */
sfr IAP_CMD     = 0xC5;            /*                                        */
sfr IAP_TRIG    = 0xC6;            /*                                        */
sfr IAP_CONTR   = 0xC7;            /*                                        */
sfr PSW         = 0xD0;            /* Program Status Word                    */
sfr ACC         = 0xE0;            /* Accumulator                            */
sfr B           = 0xF0;            /* B Register                             */


/* Bit Definitions */
/* P3 0xB0 */
sbit P3_7     = P3^7;              /*                                        */
sbit P3_6     = P3^6;              /*                                        */
sbit P3_5     = P3^5;              /*                                        */
sbit P3_4     = P3^4;              /*                                        */
sbit P3_3     = P3^3;              /*                                        */
sbit P3_2     = P3^2;              /*                                        */
sbit P3_1     = P3^1;              /*                                        */
sbit P3_0     = P3^0;              /*                                        */
sbit T1       = P3^5;              /*                                        */
sbit T0       = P3^4;              /*                                        */
sbit INT1     = P3^3;              /*                                        */
sbit INT0     = P3^2;              /*                                        */

/* PSW 0xD0 */
sbit CY       = PSW^7;             /* Carry Flag                             */
sbit AC       = PSW^6;             /* Auxiliary Carry Flag                   */
sbit F0       = PSW^5;             /* User Flag 0                            */
sbit RS1      = PSW^4;             /* Register Bank Select 1                 */
sbit RS0      = PSW^3;             /* Register Bank Select 0                 */
sbit OV       = PSW^2;             /* Overflow Flag                          */
sbit P        = PSW^0;             /* Accumulator Parity Flag                */

/* TCON  0x88 */
sbit TF1      = TCON^7;            /* Timer 1 Overflow Flag                  */
sbit TR1      = TCON^6;            /* Timer 1 On/Off Control                 */
sbit TF0      = TCON^5;            /* Timer 0 Overflow Flag                  */
sbit TR0      = TCON^4;            /* Timer 0 On/Off Control                 */
sbit IE1      = TCON^3;            /* Ext. Interrupt 1 Edge Flag             */
sbit IT1      = TCON^2;            /* Ext. Interrupt 1 Type                  */
sbit IE0      = TCON^1;            /* Ext. Interrupt 0 Edge Flag             */
sbit IT0      = TCON^0;            /* Ext. Interrupt 0 Type                  */

/*  IE 0xA8 */
sbit EA       = IE^7;              /* Global Interrupt Enable                */
sbit ELVD     = IE^6;              /*                                        */
sbit ET1      = IE^3;              /* Timer 1 Interrupt Enable               */
sbit EX1      = IE^2;              /* External Interrupt 1 Enable            */
sbit ET0      = IE^1;              /* Timer 0 Interrupt Enable               */
sbit EX0      = IE^0;              /* External Interrupt 0 Enable            */

/*  IP 0xB8 */
sbit PLVD     = IP^6;              /*                                        */
sbit PT1      = IP^3;              /* Timer 1 Priority                       */
sbit PX1      = IP^2;              /* External Interrupt 1 Priority          */
sbit PT0      = IP^1;              /* Timer 0 Priority                       */
sbit PX0      = IP^0;              /* External Interrupt 0 Priority          */


#endif                             /* #define __STC15F10_H__                 */