3.3.1 IFx Command Request Registers
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register. With this write operation the Busy bit is automatically set to ‘1’
and signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in progress. After a
wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface Register and the
Message RAM has completed. The Busy bit is set back to zero and CAN_WAIT_B is set back
to HIGH (see figure 5.2 on page 44).

Busy Busy Flag
one set to one when writing to the IFx Command Request Register
zero reset to zero when read/write action has finished.

Message Number
0x01-0x20 Valid Message Number, the Message Object in the Message
RAM is selected for data transfer.
0x00 Not a valid Message Number, interpreted as 0x20.
0x21-0x3F Not a valid Message Number, interpreted as 0x01-0x1F.

Note: When a Message Number that is not valid is written into the Command Request
Register, the Message Number will be transformed into a valid value and that Message
Object will be transferred.